1) Field of the Invention
The invention is in the field of Semiconductor Devices.
2) Description of Related Art
For the past several years, the performance of semiconductor devices, such as Metal Oxide Semiconductor Field-Effect Transistors (MOS-FETs), has been greatly enhanced by the incorporation of strained silicon regions into the active portions of a semiconductor substrate, e.g. the use of strained silicon channel regions to enhance carrier mobility. FIG. 1 depicts a typical strained MOS-FET 100 fabricated on a substrate 102. A gate dielectric layer 104 sits above a channel region 106 and a gate electrode 108 sits above gate dielectric layer 104. Gate dielectric layer 104 and gate electrode 108 are isolated by gate isolation spacers 110. Tip extensions 112 are formed by implanting dopant atoms into substrate 102. Strain-inducing source/drain regions 120 are formed by selectively growing an epitaxial film in etched-out portions of substrate 102 and are doped either in situ or after epitaxial film growth, or both. In typical MOS-FETs, the channel region 106 is comprised of crystalline silicon, while the strain-inducing source/drain regions 120 are comprised of epitaxial silicon/germanium (P-type MOSFET) or carbon-doped silicon (N-type MOS-FET) which have lattice constants different than that of crystalline silicon. Strain-inducing source/drain regions 120 can impart a uniaxial compressive (P-type) or tensile (N-type) strain to the channel region 106. Such a uniaxial strain can enhance the hole mobility or electron mobility, respectively, in channel region 106 of MOS-FET 100, lending to improved performance of the device.
FIGS. 2A-C illustrate a typical process flow for forming strain-inducing source/drain regions in a MOS-FET. Referring to FIG. 2A, a non-strained MOS-FET 200 is first formed. Non-strained MOS-FET 200 is comprised of a channel region 206. A gate dielectric layer 204 sits above the channel region 206 and a gate electrode 208 sits above gate dielectric layer 204. Gate dielectric layer 204 and gate electrode 208 are isolated by gate isolation spacer 210. Tip extensions 212 and source/drain regions 214 are formed by implanting dopant atoms into substrate 202. Thus, the source/drain regions 214 are initially formed from the same material as the channel region 206. Therefore, the lattice mismatch between the source/drain regions 214 and the channel region 206 is negligible, resulting in effectively no strain on the channel region 206.
Referring to FIG. 2B, portions of substrate 202, including source/drain regions 214, are removed, e.g. by an etch process, to form recessed regions 216 in substrate 202. Subsequently, strain-inducing silicon/germanium or carbon-doped silicon source/drain regions 220 are formed by selectively growing an epitaxial film into recessed regions 216, as depicted in FIG. 2C. Strain-inducing source/drain regions 220 can be doped with charge-carrier atoms, which may be done in situ or after epitaxial film growth, or both. In an example, substrate 202, and hence channel region 206, is comprised of crystalline silicon and the film grown to form strain-inducing source/drain regions 220 is comprised of epitaxial silicon/germanium. The lattice constant of the epitaxial silicon/germanium film can be greater than that of crystalline silicon by a factor of ˜1% (for 70% Si, 30% Ge) and so strain-inducing silicon/germanium source/drain regions 220 are comprised of a material with a larger lattice constant than that of the channel region 206.
The concentration of charge-carrier dopant impurity atoms in strain-inducing regions may play a role in the performance of MOS-FETs having such strain-inducing regions. For example, if the concentration is high, a good contact resistance may be achieved, but at the expense of short-channel effects. On the other hand, if the concentration is low, short-channel effects may be optimized, but at the expense of an increased contact resistance. Thus, multi-component strain-inducing regions, and a method to fabricate these regions, is described herein.